Different scan compression techniques have emerged for compressing scan patterns, generated using automatic test pattern generation (ATPG) tools, for reducing both test application time and test data volume for a scan core in a scan-based integrated circuit. Current scan compression techniques rely on inserting a decompressor between a limited number of compressed scan inputs and a large number of internal scan chains. The decompressor can be designed as a combinational circuit that generates decompressed scan patterns for the internal scan chains depending on the compressed scan patterns applied to the compressed scan inputs, or as a sequential circuit that can be used to generate the decompressed scan patterns for the internal scan chains based on previously stored states of the sequential elements.
Scan compression techniques utilizing a combinational decompressor typically consist of an exclusive-OR (XOR) or multiplexor (MUX) tree that may be controlled by additional control inputs or controlled by an internally stored state. See the patent by Koenemann et al. (2003) and the patent by Wang et al. (6/2009). Alternatively, a pipelined decompressor that places one or more pipelined shift registers in front of the XOR or MUX tree is used to further increase the encoding flexibility of the combinational decompressor and thus allows using only very few input pins, as low as one compressed scan input, for scan decompression. See the allowed patent by Abdel-Hafez et al. (2006/0064614), the papers co-authored by Dutta and Touba (2006), and by Chandra et al. (2009), and the patent application by Wang et al. (Ser. No. 11/889,710).
Scan compression techniques utilizing a sequential decompressor typically embed a linear-feedback shift register (LFSR) between the compressed scan inputs and internal scan chains and use the compressed scan inputs to control the LFSR in a way that makes it generate the required decompressed scan patterns, while utilizing ‘don't care’ states present in the decompressed scan patterns to reduce the complexity of the problem. See the patent by Rajski et al. (2001).
In general, scan compression techniques utilizing a sequential decompressor such as an LFSR circuit is difficult to use, requiring additional software to solve the linear equations involved in order to translate the decompressed scan patterns into the external compressed scan patterns that can be used to generate the required decompressed scan patterns through the LFSR. This results in a two-step test generation process. In some cases, these linear equations can turn out to be unsolvable, requiring multiple iterative runs where the decompressed scan patterns are reordered, duplicated, or regenerated in order to be able to generate compressed scan patterns which covers all the required faults. This can result in a significant computational overhead. In general, the compression capability of these techniques is limited since it requires that the decompressed scan patterns be generated loosely in order to guarantee that the compression equations can be solved. This results in compressing decompressed scan patterns that are sub-optimal, as opposed to compressing tightly packed decompressed scan patterns where both static and dynamic compaction are performed aggressively. Finally, any changes made to the circuit after generating the decompressed scan patterns require abandoning these patterns and going back to the beginning of the iterative process. This makes these techniques much less attractive than techniques utilizing a combinational decompressor, built mainly out of XOR or MUX gates which can utilize a one-step test generation process to automatically generate patterns that are encodable.
Current techniques utilizing a combinational decompressor or a pipelined decompressor utilize different combinational circuit designs for generating the decompressed scan patterns. In some techniques, the decompressed scan patterns are generated such that the decompressed scan patterns for each internal scan chain depends on multiple compressed scan inputs. In other techniques, the decompressed scan patterns for each internal scan chain depends on only one compressed scan input, with a few additional control inputs used to alter the relationship for different scan patterns. Finally, in some techniques, sequential elements are used in place of the additional control inputs to alter the relationship for different scan patterns. These sequential elements are typically preloaded with different data for each scan pattern. The advantage of these techniques is that the relationship between the decompressed scan patterns and the compressed scan patterns is easy to define and understand, and can be easily incorporated into the ATPG tools as part of the vector generation process, such that the compressed scan patterns are generated automatically, with dynamic compaction being aggressively applied.
The main difficulty with current decompression solutions utilizing a combinational decompressor is that the number of compressed scan inputs is typically greater than 3 to obtain an acceptable compression ratio, say 10 times, for reduction in test data volume and test application time. While a pipelined decompressor could use only one compressed scan input for scan compression, it is unclear what compression ratios in terms of test data volume and test application time one could achieve when the number of pipelined shift register stages in the pipelined decompresor is fixed.
Accordingly, there is a need to develop an improved method and apparatus for scan compression. The method in this invention is based on making the pipelined decompressor placed in front of the scan cells (scan flip-flops/latches) of the scan-based design programmable so a low-pin-count scan compression can be performed to achieve highest compression ratio.